Mentor Graphics HDL Designer Series 2015.1b 181109

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Mentor Graphics HDL Designer Series 2015.1b 181109



Mentor Graphics HDL Designer Series 2015.1b | 574 MB


Mentor Graphics Corporation, a world leader in electronic hardware and software design solutions, providing products and consulting services, has presented HDL Designer Series 2015.1b. This software combines deep analysis capabilities, advanced creation editors, and complete project and flow management, to deliver a powerful HDL design environment that increases the productivity of individual engineers and teams (local or remote) and enables a repeatable and predictable design process.The HDL Designer Series tools provide a highly automated environment for managing andexploring HDL designs. The design data is maintained as source VHDL or Verilog files which can be created or edited using HDL text or graphical editors.
The main design manager window provides library management, data exploration, and design flow control facilities. You can explore the logical or physical design objects defined by the source HDL including any associated side data objects. You can display the structure and hierarchy below any design object and compile VHDL or Verilog for individual views or hierarchies.


Structural HDL views can be rendered as a graphical block diagram or IBD view. If a state machine is defined in the source HDL code, it can be rendered as a state diagram and other nonstructural HDL can be displayed as a flow chart. New design views can be created using the HDL text or graphical editors at any level of the hierarchy.

Highlights 2015.1 (* Features included in HDL Designer, not HDL Author)

SystemVerilog Assistant*
Option to invoke outside HDL Designer (requires HDL Designer license)
Significant improvements in invocation speed and time to open large projects
New "Wrapper Import" from ModelSim/Questa compilation scripts
Updated UVM Templates
UVM 1.2 support

VHDL 2008 Enhancements
Dialect setting for graphical views
Support for Unconstrained Record Elements

Design Checking* Enhancements
Common GUI and RuleSets for RTL and verification checking
Matching Ranges rule option to ignore size mismatches of VHDL signed/unsigned expressions
Unreachable Blocks rule renamed to Reachability with new option to check for Unreachable blocks of code or conditions which are always true

Register Assistant* 4.6
RTL pipelining option
Word addressing option
UVM Endianess control
C header overall reset method

Updated Vendor Flows
New Xilinx Vivado interface

Quality Improvements
Over 65 DRs/ERs have been addressed

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the worlds most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.15 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.

Product: Mentor Graphics HDL Designer Series
Version: 2015.1b (build 4)
Supported Architectures: 32bit / 64bit
Website Home Page : www.mentor.com
Language: english
System Requirements: PC
Supported Operating Systems: ShiChuang XP / 7even

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